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1 for more information www.linear.com/ltm8073 typical a pplica t ion fea t ures descrip t ion 60v in , 3a silent switcher module regulator efficiency, v out = 5v, bias = 5v 5v out from 7v in to 60v in step-down converter a pplica t ions n power for portable products n distributed supply regulation n industrial supplies n wall transformer regulation l , lt, ltc, ltm, module, burst mode, silent switcher, linear technology and the linear logo are registered trademarks of analog devices, inc. all other trademarks are the property of their respective owners. n complete step-down switch mode power supply n low noise silent switcher ? architecture n wide input voltage range: 3.4v to 60v n wide output voltage range: 0.8v to 15v n 3a continuous output current, 24v in , 5v out , t a ?=?85c n up to 5a peak current n parallelable for increased output current n selectable switching frequency: 200khz to 3mhz n programmable soft-start n 6.25mm 9mm 3.32mm bga package the lt m ? 8073 is a 60v in , 3a (continuous) or 5a (peak) step-down silent switcher module ? (power module) regulator. included in the package are the switching con - troller, power switches, inductor, and all support compo - nents. operating over an input voltage range of 3.4v to 60v , the ltm8073 supports an output voltage range of 0.8v to 15v and a switching frequency range of 200khz to 3mhz , each set by a single resistor. only the input and output filter capacitors are needed to finish the design. the low profile package enables utilization of unused space on the bottom of pc boards for high density point of load regulation. the ltm8073 is packaged in a thermally enhanced, compact over-molded ball grid array (bga) package suitable for automated assembly by standard sur - face mount equipment. the ltm8073 is rohs compliant. 1f 100f 47.5k 32.4k 1.2mhz ltm8073 v out aux bias v out 5v 3a v in v in 7v to 60v fb gnd run sync rt 8073 ta01a pins not used in this circuit: tr/ss, pg, share ltm8073 8073fa 90 95 efficiency (%) bias = 5v 8073 ta01 v in = 24v load current (a) 0 1 2 3 80 85
2 for more information www.linear.com/ltm8073 p in c on f igura t ion a bsolu t e maxi m u m r a t ings (notes 1, 2) a 1 2 3 4 5 6 bank 2 v in top view gnd run tr/ss rt sync share pg aux bias fbgnd bank 1 gnd bank 3 v out b c d e f g h 48-lead (9mm 6.25mm 3.32mm) bga package t jmax = 125c, ja = 23.6c/w, jcbottom = 4.4c/w, jctop = 11.3c/w, jb = 2.8c/w, weight = 0.5g values determined per jedec 51-9, 51-12 v in , run voltage ...................................................... 65v p g voltage ................................................................ 42 v aux, v out , bias voltage .......................................... 19v f b, tr/ss voltage....................................................... 4v sync voltage .............................................................. 6v m aximum internal temperature (note 4) .............. 12 5 c storage temperature .............................. C 55 c to 125 c peak solder reflow (package body) temperature .. 25 0 c part number terminal finish part marking* package type msl rating temperature range (note 3) device finish code ltm8073ey#pbf sac305 (rohs) ltm8073 e1 bga 3 C40c to 125c ltm8073iy#pbf ? consult marketing for parts specified with wider operating temperature ranges. *device temperature grade is indicated by a label on the shipping container. pad or ball finish code is per ipc/jedec j-std-609. ? terminal finish part marking: www.linear.com/leadfree ? recommended bga pcb assembly and manufacturing procedures: www .linear.com/umodule/pcbassembly ? bga package and tray drawings: www.linear.com/packaging o r d er i n f or m a t ion http://www.linear.com/product/ltm8073#orderinfo ltm8073 8073fa
3 for more information www.linear.com/ltm8073 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating temperature range, otherwise specifications are at t j = 25c. v in = 12v, run = 2v, unless otherwise noted. parameter conditions min typ max units minimum input voltage v in rising l 3.4 v output dc voltage r fb open r fb = 14.3k, v in = 60v 0.8 15 v v peak output dc current v out = 3.3v, f sw = 1mhz 5 a quiescent current into v in run = 0v bias = 0v, no load, sync = 0v, not switching 3 300 a a quiescent current into bias bias = 5v, run = 0v bias = 5v, no load, sync = 0v, not switching bias = 5v, v out = 3.3v, i out = 3a, f sw = 1mhz 1 275 12 a a ma line regulation 5.5v < v in < 36v, i out = 1a 0.5 % load regulation 0.1a < i out < 3a 0.5 % output voltage ripple i out = 3a 10 mv switching frequency r t = 232k r t = 41.2k r t = 10.7k 200 0.95 3 khz mhz mhz voltage at fb l 772 802 817 mv minimum bias voltage (note 5) 3.2 v run threshold voltage 0.9 1.06 v run current 1 a tr/ss current tr/ss = 0v 2 a tr/ss pull-down tr/ss = 0.1v 200 pg threshold voltage at fb (upper) fb falling (note 6) 0.88 v pg threshold voltage at fb (lower) fb rising (note 6) 0.73 v pg leakage current pg = 42v 1 a pg sink current pg = 0.1v 150 a sync threshold voltage synchronization 0.4 1.5 v sync voltage to enable spread spectrum 2.9 4.2 v sync current sync = 0v 35 a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: unless otherwise noted, the absolute minimum voltage is zero. note 3: the ltm8073e is guaranteed to meet performance specifications from 0c to 125c internal. specifications over the full C40c to 125c internal operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltm8073i is guaranteed to meet specifications over the full C40c to 125c internal operating temperature range. note that the maximum internal temperature is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. note 4: the ltm8073 contains overtemperature protection that is intended to protect the device during momentary overload conditions. the internal temperature exceeds the maximum operating junction temperature when the overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 5. below this specified voltage, internal circuitry will draw power from v in . note 6. pg transitions from low to high. ltm8073 8073fa
4 for more information www.linear.com/ltm8073 typical p er f or m ance c harac t eris t ics efficiency, v out = 0.8v, bias?=?5v efficiency, v out = 1v, bias?=?5v efficiency, v out ?=?1.2v, bias?=?5v efficiency, v out ?=?1.5v, bias?=?5v efficiency, v out ?=?1.8v, bias?=?5v efficiency, v out ?=?2v, bias?=?5v efficiency, v out ?=?2.5v, bias?=?5v efficiency, v out ?=?3.3v, bias?=?5v efficiency, v out ?=?5v, bias?=?5v t a = 25c, unless otherwise noted. ltm8073 8073fa 3 85 95 efficiency (%) 8073 g06 12v in 24v in 36v in 4 48v in load current (a) 0 1 2 3 4 55 65 50 75 85 95 efficiency (%) 8073 g07 12v in 24v in 36v 60 in 48v in load current (a) 0 1 2 3 4 55 70 65 75 85 95 efficiency (%) 8073 g08 12v in 24v in 36v in 48v in 80 load current (a) 0 1 2 3 4 55 65 75 85 90 95 efficiency (%) 8073 g09 efficiency (%) 8073 g01 12v in 12v in 24v in 36v in 48v in load current (a) 0 1 2 3 4 50 24v in 60 70 80 90 efficiency (%) 8073 g02 12v in 24v in 36v in 48v in 36v in load current (a) 0 1 2 3 4 50 60 70 80 48v in 90 efficiency (%) 8073 g03 12v in 24v in 36v in 48v in load current (a) 0 1 load current (a) 2 3 4 50 60 70 80 90 efficiency (%) 8073 g04 0 12v in 24v in 36v in 48v in load current (a) 0 1 2 3 4 1 55 65 75 85 95 efficiency (%) 8073 g05 12v in 24v in 36v in 2 48v in load current (a) 0 1 2 3 4 55 65 75
5 for more information www.linear.com/ltm8073 typical p er f or m ance c harac t eris t ics efficiency, v out ?=?8v, bias?=?5v efficiency, v out ?=?12v, bias?=?5v efficiency, v out ?=?15v, bias?5v efficiency, v out ?=?C3.3v, bias tied to ltm8073 gnd efficiency, v out ?=?C5v, bias tied to ltm8073 gnd efficiency, v out ?=?C8v, bias tied to ltm8073 gnd efficiency, v out ?=?C12v, bias tied to ltm8073 gnd t a = 25c, unless otherwise noted. efficiency, v out ?=?C15v, bias tied to ltm8073 gnd input vs load current v out ?=?0.8v ltm8073 8073fa 3 in 24v in 36v in 48v in load current (a) 0 1 4 2 3 50 60 70 80 90 efficiency (%) 8073 g15 12v in 60 24v in 36v in 48v in load current (a) 0 1 2 3 50 60 70 70 80 90 efficiency (%) 8073 g16 12v in 24v in 36v in load current (a) 0 80 1 2 50 60 70 80 90 efficiency (%) 8073 g17 12v in 90 24v in 36v in 48v in load current (a) 0 1 2 3 4 5 100 0 0.25 0.50 0.75 input current (a) 8073 g18 efficiency (%) 8073 g10 24v 12v in in 36v in 48v in load current (a) 0 1 2 3 24v in 4 60 70 80 90 100 efficiency (%) 8073 g11 24v in 36v in 36v in 48v in load current (a) 0 1 2 3 4 48v in 60 70 80 90 100 efficiency (%) 8073 g12 12v in 24v load current (a) in 36v in 48v in load current (a) 0 1 2 3 0 4 50 60 70 80 90 efficiency (%) 8073 g13 12v in 1 24v in 36v in 48v in load current (a) 0 1 2 2 3 4 50 60 70 80 90 efficiency (%) 8073 g14 12v
6 for more information www.linear.com/ltm8073 typical p er f or m ance c harac t eris t ics input vs load current v out ?=?1v input vs load current v out ?=?1.2v input vs load current v out ?=?1.5v input vs load current v out ?=?1.8v input vs load current v out ?=?2.5v input vs load current v out ?=?3.3v input vs load current v out ?=?5v input vs load current v out ?=?8v input vs load current v out ?=?12v t a = 25c, unless otherwise noted. ltm8073 8073fa 3 0 0.5 1.0 1.5 2.0 input current (a) 8073 g24 12v in 24v in 36v in 4 48v in load current (a) 0 1 2 3 4 5 0 0.5 5 1.0 1.5 2.0 2.5 input current (a) 8073 g25 12v in 24v in 36v in 48v in 0 load current (a) 0 1 2 3 4 5 0 1.0 2.0 0.25 3.0 4.0 input current (a) 8073 g26 24v in 36v in 48v in load current (a) 0 1 0.50 2 3 4 5 0 1 2 3 input current (a) 8073 g27 0.75 input current (a) 8073 g19 12v in 12v in 24v in 36v in 48v in load current (a) 0 1 2 3 4 5 24v in 0 0.25 0.50 0.75 1.00 input current (a) 8073 g20 12v in 24v in 36v in 36v in 48v in load current (a) 0 1 2 3 4 5 0 0.25 48v in 0.50 0.75 1.00 input current (a) 8073 g21 12v in 24v in 36v in 48v in load current (a) load current (a) 0 1 2 3 4 5 0 0.5 1.0 1.5 0 input current (a) 8073 g22 12v in 24v in 36v in 48v in load current (a) 0 1 2 1 3 4 5 0 0.5 1.0 1.5 input current (a) 8073 g23 12v in 2 24v in 36v in 48v in load current (a) 0 1 2 3 4 5
7 for more information www.linear.com/ltm8073 typical p er f or m ance c harac t eris t ics input vs load current v out ?=?15v input vs load current v out ?=?C3.3v input vs load current v out ?=?C5v input vs load current v out ?=?C8v input vs load current v out ?=?C12v t a = 25c, unless otherwise noted. input vs load current v out ?=?C15v i bias vs switching frequency v bias ?=?5v, v in = 24v dropout voltage vs load current v out ?=?5v, bias?open input current vs v in v out ?shorted, dc2389 a eval board ltm8073 8073fa 4 switching frequency (mhz) 0 1 2 3 0 4 8 12 16 5 20 bias current (ma) 8073 g34 load current (a) 0 1 2 3 4 5 0 0 500 1000 1500 dropout voltage (mv) 8073 g35 input voltage (v) 0 10 20 1 30 40 0 0.5 1.0 1.5 2.0 input current (a) 8073 g36 2 3 input current (a) 8073 g28 12v in 24v in 24v in 36v in 48v in load current (a) 0 1 2 3 4 5 0 36v in 0.50 1.00 1.50 input current (a) 8073 g29 12v in 24v in 36v in 48v in load current (a) 48v in 0 1 2 3 4 0 0.5 1.0 1.5 2.0 load current (a) input current (a) 8073 g30 12v in 24v in 36v in 48v in load current (a) 0 1 2 0 3 0 0.5 1.0 1.5 2.0 input current (a) 8073 g31 12v in 24v in 1 36v in 48v in load current (a) 0 1 2 3 0 0.5 1.0 2 1.5 2.0 2.5 input current (a) 8073 g32 12v in 24v in 36v in load current (a) 0 3 1 2 0 0.5 1.0 1.5 2.0 2.5 input current (a) 8073 g33
8 for more information www.linear.com/ltm8073 typical p er f or m ance c harac t eris t ics maximum load current vs v in bias tied to ltm8073 gnd maximum load current vs v in bias tied to ltm8073 gnd derating, v out ?=?0.8v, bias?=?5v, dc2389a demo board derating, v out ?=?1v, bias?=?5v, dc2389a demo board derating, v out ?=?1.2v, bias?=?5v, dc2389a demo board derating, v out ?=?1.5v, bias?=?5v, dc2389a demo board derating, v out ?=?1.8v, bias?=?5v, dc2389a demo board derating, v out ?=?2.5v, bias?=?5v, dc2389a demo board derating, v out ?=?3.3v, bias?=?5v, dc2389a demo board t a = 25c, unless otherwise noted. 12v in 24v in 36v in 48v in 12v in 24v in 36v in 48v in 12v in 24v in 36v in 48v in 12v in 24v in 36v in 48v in 12v in 24v in 36v in 48v in 12v in 24v in 36v in 48v in 12v in 24v in 36v in 48v in ltm8073 8073fa 0 50 75 100 125 0 1 2 3 4 5 1 maximum load current (a) 8073 g43 ambient temperature (c) 0 lfm 0 25 50 75 100 125 2 0 1 2 3 4 5 maximum load current (a) 8073 g44 ambient temperature (c) 0 lfm 3 ambient temperature (c) 0 25 50 75 100 125 0 1 2 4 3 4 5 maximum load current (a) 8073 g45 5 maximum load current (a) 8073 g37 ?12v out ?15v out ?3.3v out input voltage (v) 0 20 40 60 0 1 2 3 maximum load current (a) ?5v out 8073 g38 0 lfm ambient temperature ( o c) 0 25 50 75 100 ?8v out 125 0 1 2 3 4 5 maximum load current (a) 8073 g39 0 lfm input voltage (v) 0 25 50 75 100 125 0 1 2 3 0 4 5 maximum load current (a) 8073 g40 ambient temperature (c) 0 lfm 0 25 50 75 20 100 125 0 1 2 3 4 5 maximum load current (a) 8073 g41 40 ambient temperature (c) 0 lfm 0 25 50 75 100 125 0 1 60 2 3 4 5 maximum load current (a) 8073 g42 ambient temperature (c) 0 lfm 0 25
9 for more information www.linear.com/ltm8073 typical p er f or m ance c harac t eris t ics derating, v out ?=?5v, bias?=?5v, dc2389a demo board derating, v out ?=?8v, bias?=?5v, dc2389a demo board derating, v out ?=?15v, bias?=?5v, dc2389a demo board derating, v out ?=?C3.3v, bias tied to ltm8073 gnd, dc2389a demo board derating, v out ?=?12v, bias?=?5v, dc2389a demo board t a = 25c, unless otherwise noted. 12v in 24v in 36v in 48v in 12v in 24v in 36v in 48v in 24v in 36v in 48v in 24v in 36v in 48v in 12v in 24v in 36v in 48v in derating, v out ?=?C5v, bias tied to ltm8073 gnd, dc2389a demo board 12v in 24v in 36v in 48v in derating, i-grade v out ?=?C8v, bias tied to ltm8073 gnd, dc2389a demo board 12v in 24v in 36v in 48v in derating, i-grade v out ?=?C12v, bias tied to ltm8073 gnd, dc2389a demo board 12v in 24v in 36v in 48v in derating, i-grade v out ?=?C15v, bias tied to ltm8073 gnd, dc2389a demo board 12v in 24v in 36v in ltm8073 8073fa 1 0 1 2 3 maximum load current (a) 8073 g52 ambient temperature (c) 0 lfm 0 25 2 50 75 100 125 0 0.5 1.0 1.5 2.0 maximum load current (a) 3 8073 g53 ambient temperature (c) 0 lfm ambient temperature (c) 0 25 50 75 100 125 4 0 0.5 1.0 1.5 2.0 maximum load current (a) 8073 g54 5 maximum load current (a) 8073 g46 ambient temperature (c) 0 lfm ambient temperature (c) 0 lfm 0 25 50 75 100 125 0 1 2 3 0 4 5 maximum load current (a) 8073 g47 0 lfm 0 25 50 75 100 25 125 0 1 2 3 4 maximum load current (a) 8073 g48 ambient temperature (c) 0 lfm 50 0 25 50 75 100 125 0 1 2 3 75 4 maximum load current (a) 8073 g49 ambient temperature (c) 0 lfm 0 25 50 75 100 100 125 0 1 2 3 4 maximum load current (a) 8073 g50 ambient temperature (c) 0 lfm 125 0 25 50 75 100 125 0 1 2 3 0 maximum load current (a) 8073 g51 ambient temperature (c) 0 lfm 0 25 50 75 100 125
10 for more information www.linear.com/ltm8073 typical p er f or m ance c harac t eris t ics cispr22 class b radiated dc2389a demo board, v out = 5v no filter (fb1 short, c8, c9 open) cispr22 class b radiated dc2389a demo board, v out = 5v no filter (fb1 short, c8, c9 open) t a = 25c, unless otherwise noted. p in func t ions gnd (bank 1, a1, a6, b3 ): tie these gnd pins to a local ground plane below the ltm8073 and the circuit components. in most applications, the bulk of the heat flow out of the ltm8073 is through these pads, so the printed circuit design has a large impact on the ther - mal performance of the part. see the pcb layout and thermal considerations sections for more details. v in (bank 2): v in supplies current to the ltm8073 s internal regulator and to the internal power switch. these pins must be locally bypassed with an external, low esr capacitor; see table 1 for recommended values. v out (bank 3): power output pins. apply the output filter capacitor and the output load between these pins and gnd pins. bias (pin a2 ): the bias pin connects to the internal power bus. connect to a power source greater than 3.2v. if v out is greater than 3.2v , connect this pin to aux. decouple this pin with at least 1f if the voltage source for bias is remote. pg (pin a3 ): the pg pin is the open-collector output of an internal comparator. pg remains low until the fb pin voltage is between 0.73v and 0.88v typical. the pg signal is valid when v in is above 3.4v. if v in is above 3.4v and run is low, pg will drive low. if this function is not used, leave this pin floating. share (pin a4): tie this to the share pin of another ltm8073 to load share. otherwise leave floating. do not drive this pin. rt (pin a5 ): the rt pin is used to program the switching frequency of the ltm8073 by connecting a resistor from this pin to ground. the applications information section of the data sheet includes a table to determine the resis - tance value based on the desired switching frequency. minimize capacitance at this pin. do not drive this pin. fb (pin b1): the ltm8073 regulates its fb pin to 0.8v. connect the adjust resistor from this pin to ground. the value of r fb is given by the equation r fb = 199.7/(v out C 0.8), where r fb is in k. ltm8073 8073fa 600 800 1000 ?10 0 10 20 30 40 50 f sw = 1.2mhz, v in = 28v, i out = 3.5a amplitude (dbuv/m) 8073 g55 f sw = 1.2mhz, v in = 14v, i out = 3.5a class b limit horizontal vertical frequency (mhz) 0 200 400 class b limit 600 800 1000 ?10 0 10 20 30 40 50 horizontal amplitude (dbuv/m) 8073 g56 vertical frequency (mhz) 0 200 400
11 for more information www.linear.com/ltm8073 p in func t ions aux (pin b2 ): low current voltage source for bias. in many designs, the bias pin is simply connected to v out . the aux pin is internally connected to v out and is placed adjacent to the bias pin to ease printed cir - cuit board routing. also, some applications require a feed-forward capacitor ; it can be connected from aux to fb for convenient pcb routing. although this pin is internally connected to v out , it is not intended to deliver a high current, so do not draw current from this pin to the load. sync (pin b4 ): external clock synchronization input and operational mode. this pin programs four different operating modes: 1) burst mode ? . tie this pin to ground for burst mode operation at low output loads this will result in low quiescent current. 2) pulse-skipping mode. float this pin for pulse-skipping mode. this mode offers full frequency operation down to low output loads before pulse-skipping mode occurs. 3) spread spectrum mode. tie this pin high (between 2.9v and 4.2v ) for pulse-skipping mode with spread spectrum modulation. 4) synchronization mode. drive this pin with a clock source to synchronize to an external frequency. during synchronization the part will operate in pulse-skipping mode. tr/ss (pin b5 ): the tr/ss pin is used to provide a soft-start or tracking function. the internal 2a pull-up current in combination with an external capacitor tied to this pin creates a voltage ramp. if tr/ss is less than 0.8v, the fb voltage tracks to this value. for tracking, tie a resistor divider to this pin from the tracked output. this pin is pulled to ground with an internal mosfet during shutdown and fault conditions; use a series resistor if driving from a low impedance output. this pin may be left floating if the tracking function is not needed. run (pin b6 ): pull the run pin below 0.9v to shut down the ltm8073 . tie to 1.06v or more for normal opera - tion. if the shutdown feature is not used, tie this pin to the v in pin. b lock diagra m aux bias v out v in fb gnd run share tr/ss sync rt pg 8073 bd current mode controller 0.2f 10pf 0.1f 249k 2.2h ltm8073 8073fa
12 for more information www.linear.com/ltm8073 o pera t ion the ltm8073 is a standalone nonisolated step-down switching dc/dc power supply that can deliver up to 5a. the continuous current is determined by the internal oper - ating temperature. it provides a precisely regulated output voltage programmable via one external resistor from 0.8v to 15v . the input voltage range is 3.4v to 60v. given that the ltm8073 is a step-down converter, make sure that the input voltage is high enough to support the desired output voltage and load current. a simplified block diagram is given on the previous page. the ltm8073 contains a current mode controller, power switching elements, power inductor and a modest amount of input and output capacitance. the ltm8073 is a fixed frequency pwm regulator. the switching frequency is set by simply connecting the appropriate resistor value from the rt pin to gnd. an internal regulator provides power to the control cir - cuitry. this bias regulator normally draws power from the v in pin, but if the bias pin is connected to an external voltage higher than 3.2v, bias power is drawn from the external source (typically the regulated output voltage). this improves efficiency. the run pin is used to place the ltm8073 in shutdown, disconnecting the output and reducing the input current to a few a. to enhance efficiency, the ltm8073 automatically switches to burst mode operation in light or no load situations. between bursts, all circuitry associated with controlling the output switch is shut down reducing the input supply current. the oscillator reduces the ltm8073 s operating frequency when the voltage at the fb pin is low. this frequency fold - back helps to control the output current during start-up and overload. the tr/ss node acts as an auxiliary input to the error amplifier. the voltage at fb servos to the tr/ss voltage until tr/ss goes above about 0.8v. soft-start is imple - mented by generating a voltage ramp at the tr/ss pin using an external capacitor which is charged by an internal constant current. alternatively, driving the tr/ss pin with a signal source or resistive network provides a tracking function. do not drive the tr/ss pin with a low imped - ance voltage source. see the applications information section for more details. the ltm8073 contains a power good comparator which trips when the fb pin is between 0.73v and 0.88v , typical. the pg output is an open-drain transistor that is off when the output is in regulation, allowing an external resistor to pull the pg pin high. the pg signal is valid when v in is above 3.4v. if v in is above 3.4v and run is low, pg will drive low. the ltm8073 is equipped with a thermal shutdown that inhibits power switching at high junction temperatures. the activation threshold of this function is above 125 c to avoid interfering with normal operation, so prolonged or repetitive operation under a condition in which the thermal shutdown activates may damage or impair the reliability of the device. ltm8073 8073fa
13 for more information www.linear.com/ltm8073 a pplica t ions i n f or m a t ion for most applications, the design process is straight- forward, summarized as follows: 1. look at table 1 and find the row that has the desired input range and output voltage. 2. apply the recommended c in , c out , r fb and r t values. 3. apply the c ff (from aux to fb) capacitor as required. 4. connect bias as indicated. while these component combinations have been tested for proper operation, it is incumbent upon the user to verify proper operation over the intended system s line, load and environmental conditions. bear in mind that the maximum output current is limited by junction temperature, the relationship between the input and output voltage mag - nitude and polarity and other factors. please refer to the graphs in the typical performance characteristics section for guidance. the maximum frequency (and attendant r t value) at which the ltm8073 should be allowed to switch is given in table 1 in the maximum f sw column, while the recom - mended frequency (and r t value) for optimal efficiency over the given input condition is given in the f sw column. there are additional conditions that must be satisfied if the synchronization function is used. please refer to the synchronization section for details. table 1. recommended component values and configuration (t a = 25c) v in (note 1) v out r fb c in (note 2) c out c ff bias f sw r t max f sw min r t 3.4v to 60v 0.8v open 1f 100v 1206 x7r 2 100f 4v 0805 x5r 47pf 5v 450khz 95.3k 475khz 90.9k 3.4v to 60v 1v 1m 1f 100v 1206 x7r 2 100f 4v 0805 x5r 47pf 5v 450khz 95.3k 550khz 76.8k 3.4v to 60v 1.2v 499k 1f 100v 1206 x7r 2 100f 4v 0805 x5r 47pf 5v 500khz 84.5k 650khz 63.4k 3.4v to 60v 1.5v 287k 1f 100v 1206 x7r 100f 4v 0805 x5r 27pf 5v 500khz 84.5k 750khz 54.9k 3.4v to 60v 1.8v 200k 1f 100v 1206 x7r 100f 4v 0805 x5r 10pf 5v 500khz 84.5k 900khz 45.6k 3.4v to 60v 2v 169k 1f 100v 1206 x7r 100f 4v 0805 x5r 5v 600khz 64.8k 950khz 42.2k 4v to 60v 2.5v 118k 1f 100v 1206 x7r 100f 4v 0805 x5r 5v 800khz 51.1k 1.2mhz 32.4k 5v to 60v 3.3v 80.6k 1f 100v 1206 x7r 100f 4v 0805 x5r 5v 850khz 47.5k 1.5mhz 24.3k 7v to 60v 5v 47.5k 1f 100v 1206 x7r 100f 6.3v 1206 x5r 5v 1.2mhz 32.4k 2.2mhz 16.9k 11v to 60v 8v 28k 1f 100v 1206 x7r 47f 16v 1210 x7r 5v 1.4mhz 26.7k 3mhz 10k 16v to 60v 12v 17.8k 1f 100v 1206 x7r 22f 25v 1210 x5r 5v 1.4mhz 26.7k 3mhz 10k 19.5v to 60v 15v 14.3k 1f 100v 1206 x7r 22f 25v 1210 x5r 5v 1.4mhz 26.7k 3mhz 10k 3.4v to 56v C3.3v 80.6k 1f 100v 1206 x7r 100f 4v 0805 x5r ltm8073 gnd 850khz 47.5k 1.5mhz 24.3k 3.4v to 55v C5v 47.5k 1f 100v 1206 x7r 100f 6.3v 1206 x5r ltm8073 gnd 1.2mhz 32.4k 2.2mhz 16.9k 3.4v to 52v C8v 28k 1f 100v 1206 x7r 47f 16v 1210 x7r ltm8073 gnd 1.4mhz 26.7k 3mhz 10k 3.4v to 48v C12v 17.8k 1f 100v 1206 x7r 22f 25v 1210 x5r ltm8073 gnd 1.4mhz 26.7k 3mhz 10k 3.4v to 45v C15v 14.3k 1f 100v 1206 x7r 22f 25v 1210 x5r ltm8073 gnd 1.4mhz 26.7k 3mhz 10k note 1: the ltm8073 may be capable of lower input voltages but may skip switching cycles. note 2: an input bulk capacitor is required. ltm8073 8073fa
14 for more information www.linear.com/ltm8073 a pplica t ions i n f or m a t ion capacitor selection considerations the c in and c out capacitor values in table 1 are the mini - mum recommended values for the associated operating conditions. applying capacitor values below those indi - cated in table 1 is not recommended, and may result in undesirable operation. using larger values is generally acceptable, and can yield improved dynamic response, if it is necessary. again, it is incumbent upon the user to verify proper operation over the intended systems line, load and environmental conditions. ceramic capacitors are small, robust and have very low esr. however, not all ceramic capacitors are suitable. x5r and x7r types are stable over temperature and applied voltage and give dependable service. other types, includ - ing y5v and z5u have very large temperature and voltage coefficients of capacitance. in an application circuit they may have only a small fraction of their nominal capaci - tance resulting in much higher output voltage ripple than expected. ceramic capacitors are also piezoelectric. in burst mode operation, the ltm8073 s switching frequency depends on the load current, and can excite a ceramic capacitor at audio frequencies, generating audible noise. since the ltm8073 operates at a lower current limit during burst mode operation, the noise is typically very quiet to a casual ear. if this audible noise is unacceptable, use a high perfor - mance electrolytic capacitor at the output. it may also be a parallel combination of a ceramic capacitor and a low cost electrolytic capacitor . a final precaution regarding ceramic capacitors concerns the maximum input voltage rating of the ltm8073 . a ceramic input capacitor combined with trace or cable inductance forms a high-q (underdamped) tank circuit. if the ltm8073 circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possi - bly exceeding the devices rating. this situation is easily avoided; see the hot-plugging safely section. frequency selection the ltm8073 uses a constant frequency pwm architec - ture that can be programmed to switch from 200khz to 3mhz by using a resistor tied from the r t pin to ground. table?2 provides a list of r t resistor values and their resul - tant frequencies. table 2. sw frequency vs r t value f sw (mhz) r t (k) 0.2 232 0.3 150 0.4 110 0.5 84.5 0.6 64.8 0.7 60.4 0.8 51.1 1.0 40.2 1.2 32.4 1.4 28.0 1.6 23.7 1.8 20.5 2.0 16.9 2.2 15.8 3.0 10 operating frequency trade-offs it is recommended that the user apply the optimal r t value given in table 1 for the input and output oper - ating condition. system level or other considerations, however, may necessitate another operating frequency. while the ltm8073 is flexible enough to accommodate a wide range of operating frequencies, a haphazardly chosen one may result in undesirable operation under certain operating or fault conditions. a frequency that is too high can reduce efficiency, generate excessive heat or even damage the ltm8073 if the output is overloaded or short-circuited. a frequency that is too low can result in a final design that has too much output ripple or too large of an output capacitor. ltm8073 8073fa
15 for more information www.linear.com/ltm8073 a pplica t ions i n f or m a t ion bias pin considerations the bias pin is used to provide drive power for the inter - nal power switching stage and operate other internal cir - cuitry. for proper operation, it must be powered by at least 3.2v . if the output voltage is programmed to 3.2v or higher, bias may be simply tied to aux . if v out is less than 3.2v , bias can be tied to v in or some other voltage source. if the bias pin voltage is too high, the efficiency of the ltm8073 may suffer. the optimum bias voltage is dependent upon many factors, such as load current, input voltage, output voltage and switching frequency. in all cases, ensure that the maximum voltage at the bias pin is less than 19v. if bias power is applied from a remote or noisy voltage source, it may be necessary to apply a decoupling capacitor locally to the pin. a 1f ceramic capacitor works well. the bias pin may also be left open at the cost of a small degradation in efficiency. if the ltm8073 is configured to provide a negative output, do not connect bias to v out or aux. instead, tie to bias to the ltm8073 gnd, which should be the negative output. maximum load the maximum practical continuous load that the ltm8073 can drive, while rated at 3a, actually depends upon both the internal current limit and the internal temperature. the internal current limit is designed to prevent damage to the ltm8073 in the case of overload or short-circuit. the internal temperature of the ltm8073 depends upon operating conditions such as the ambient temperature, the power delivered, and the heat sinking capability of the system. for example, if the ltm8073 is configured to reg - ulate at 1.2v , it may continuously deliver 4.5a from 12v in if the ambient temperature is controlled to less than 55 c; this is more than the 3a continuous rating. please see the derating curve for v out = 1.2v in the typical performance characteristics section. similarly, if the output voltage is 15v and the ambient temperature is 95c, the ltm8073 will deliver at most 2a from 24v in , which is less than the 3a continuous rating. load sharing ltm8073s may be paralleled to produce higher currents. to do this, tie the v in , v out and share pins of all the paralleled ltm8073 s together. to ensure that paralleled modules start up together, the tr/ss pins may be tied together, as well. if it is inconvenient to tie the tr/ss pins together, make sure that the same valued soft-start capac - itors are used for each module regulator. an example of two ltm8073 s configured for load sharing is given in the typical applications section. for closer load sharing, synchronize the ltm8073s to an external clock source. when load sharing among n units and using a single r fb resistor, the value of the resistor is : r fb = 199.7 n v out C 0.8 ( ) where r fb is in k. burst mode operation to enhance efficiency at light loads, the ltm8073 auto - matically switches to burst mode operation which keeps the output capacitor charged to the proper voltage while minimizing the input quiescent current. during burst mode operation, the ltm8073 delivers single cycle bursts of current to the output capacitor followed by sleep peri - ods where most of the internal circuitry is powered off and energy is delivered to the load by the output capacitor. during the sleep time, v in and bias quiescent currents are greatly reduced, so, as the load current decreases towards a no load condition, the percentage of time that the ltm8073 operates in sleep mode increases and the average input current is greatly reduced, resulting in higher light load efficiency. burst mode operation is enabled by tying sync to gnd. minimum input voltage the ltm8073 is a step-down converter, so a minimum amount of headroom is required to keep the output in regulation. keep the input above 3.4v to ensure proper operation. voltage transients or ripple valleys that cause the input to fall below 3.4v may turn off the ltm8073. output voltage tracking and soft-start the ltm8073 allows the user to program its output volt - age ramp rate by means of the tr/ss pin. an internal 2a ltm8073 8073fa
16 for more information www.linear.com/ltm8073 a pplica t ions i n f or m a t ion pulls up the tr/ss pin to about 2.4v . putting an external capacitor on tr/ss enables soft starting the output to reduce current surges on the input supply. during the soft- start ramp the output voltage will proportionally track the tr/ss pin voltage. for output tracking applications, tr/ss can be externally driven by another voltage source. from 0v to 0.8v , the tr/ss voltage will override the internal 0.8v reference input to the error amplifier, thus regulating the fb pin voltage to that of the tr/ss pin. when tr/ss is above 0.8v , tracking is disabled and the feedback voltage will regulate to the internal reference voltage. the tr/ss pin may be left floating if the function is not needed. an active pull-down circuit is connected to the tr/ss pin which will discharge the external soft-start capacitor in the case of fault conditions and restart the ramp when the faults are cleared. fault conditions that clear the soft-start capacitor are the run pin transitioning low, v in voltage falling too low, or thermal shutdown. prebiased output as discussed in the output voltage tracking and soft-start section, the ltm8073 regulates the output to the fb volt - age determined by the tr/ss pin whenever tr/ss is less than 0.8v . if the ltm8073 output is higher than the target output voltage, the ltm8073 will attempt to regulate the output to the target voltage by returning a small amount of energy back to the input supply. if there is nothing load - ing the input supply, its voltage may rise. take care that it does not rise so high that the input voltage exceeds the absolute maximum rating of the ltm8073. frequency foldback the ltm8073 is equipped with frequency foldback which acts to reduce the thermal and energy stress on the inter - nal power elements during a short-circuit or output over - load condition. if the ltm8073 detects that the output has fallen out of regulation, the switching frequency is reduced as a function of how far the output is below the target voltage. this in turn limits the amount of energy that can be delivered to the load under fault. during the start-up time, frequency foldback is also active to limit the energy delivered to the potentially large output capaci - tance of the load. when a clock is applied to the sync pin, the sync pin is floated or held high, the frequency foldback is disabled and the switching frequency will slow down only during overcurrent conditions. synchronization to select low ripple burst mode operation, tie the sync pin below about 0.4v (this can be ground or a logic low output). to synchronize the ltm8073 oscillator to an external frequency connect a square wave (with about 20% to 80% duty cycle) to the sync pin. the square wave amplitude should have valleys that are below 0.4v and peaks above 1.5v. the ltm8073 will not enter burst mode operation at low output loads while synchronized to an external clock, but instead will pulse skip to maintain regulation. the ltm8073 may be synchronized over a 200khz to 3mhz range. the r t resistor should be chosen to set the ltm8073 switching frequency equal to or below the lowest synchronization input. for example, if the synchronization signal will be 500khz and higher, the r t should be selected for 500khz. for some applications it is desirable for the ltm8073 to operate in pulse-skipping mode, offering two major dif - ferences from burst mode operation. the first is that the clock stays awake at all times and all switching cycles are aligned to the clock. second is that full switching fre - quency is reached at lower output load than in burst mode operation. these two differences come at the expense of increased quiescent current. to enable pulse-skipping mode, the sync pin is floated. the ltm8073 features spread spectrum operation to fur - ther reduce emi/emc emissions. to enable spread spec - trum operation, apply between 2.9v and 4.2v to the sync pin. in this mode, triangular frequency modulation is used to vary the switching frequency between the value pro - grammed by r t to about 20% higher than that value. the modulation frequency is about 3khz. for example, when the ltm8073 is programmed to 2mhz, the frequency will vary from 2mhz to 2.4mhz at a 3khz rate. when spread spectrum operation is selected, burst mode operation is disabled, and the part will run in pulse-skipping mode. the ltm8073 does not operate in forced continuous mode regardless of sync signal. ltm8073 8073fa
17 for more information www.linear.com/ltm8073 figure 1a. the ltm8073 can be used to generate a negative voltage a pplica t ions i n f or m a t ion negative output the ltm8073 is capable of generating a negative output voltage by connected its v out to system gnd and the ltm8073 gnd to the negative voltage rail. an example of this is shown in the typical applications section. the most versatile way to generate a negative output is to use a dedicated regulator that was designed to generate a negative voltage, but using a buck regulator like the ltm8073 to generate a negative voltage is a simple and cost effective solution, as long as certain restrictions are kept in mind. figure 1a shows a typical negative output voltage applica - tion. note that ltm8073 v out is tied to system gnd and input power is applied from v in to ltm8073 v out . as a result, the ltm8073 is not behaving as a true buck regu - lator, and the maximum output current is depends upon the input voltage. in the example shown in the typical applications section, there is an attending graph that shows how much current the ltm8073 deliver for given input voltages. the c in and c out capacitors in figure 1c form an ac divider at the negative output voltage node. if v in is hot- plugged or rises quickly, the resultant v out will be a posi - tive transient, which may be unhealthy for the application load. an antiparallel schottky diode may be able to pre- vent this positive transient from damaging the load. the location of this schottky diode is important. for example, in a system where the ltm8073 is far away from the load, placing the schottky diode closest to the most sensitive load component may be the best design choice. carefully evaluate whether the negative buck configuration is suit - able for the application. note that this configuration requires that any load current transient will directly impress the transient voltage onto the ltm8073 gnd, as shown in figure 1b, so fast load transients can disrupt the ltm8073s operation or even cause damage. carefully evaluate whether the negative buck configuration is suitable for the application. negative output voltage ltm8073 v out v in 8073 f01a gnd v in fast load transient output transient response ltm8073 v out v in 8073 f01b gnd v in fast v in transient output experiences a positive transient ltm8073 v out v in 8073 f01c gnd c out c in optional schottky diode ac divider v in figure 1b. any output voltage transient appears on ltm8073 gnd figure 1c. a schottky diode can limit the transient caused by a fast rising v in to safe levels if the ltm8073 is configured to provide a negative output, do not connect bias to v out or aux. instead, tie to bias to the ltm8073 gnd, which should be the negative output. ltm8073 8073fa
18 for more information www.linear.com/ltm8073 a pplica t ions i n f or m a t ion shorted input protection care needs to be taken in systems where the output is held high when the input to the ltm8073 is absent. this may occur in battery charging applications or in battery backup systems where a battery or some other supply is diode or-ed with the ltm8073s output. if the v in pin is allowed to float and the run pin is held high (either by a logic signal or because it is tied to v in ), then the ltm8073 s internal circuitry pulls its quiescent current through its internal power switch. this is fine if your system can tolerate a few milliamps in this state. if you ground the run pin, the internal current drops to essen - tially zero. however, if the v in pin is grounded while the output is held high, parasitic diodes inside the ltm8073 can pull large currents from the output through the v in pin. figure 2 shows a circuit that runs only when the input voltage is present and that protects against a shorted or reversed input. minimize emi and ensure proper operation. even with the high level of integration, you may fail to achieve specified operation with a haphazard or poor layout. see figure 3 for a suggested layout. ensure that the grounding and heat sinking are acceptable. a few rules to keep in mind are: 1. place c ff , r fb and r t as close as possible to their respective pins. 2. place the c in capacitor as close as possible to the v in and gnd connection of the ltm8073. 3. place the c out capacitor as close as possible to the v out and gnd connection of the ltm8073. 4. place the c in and c out capacitors such that their ground current flow directly adjacent to or underneath the ltm8073. 5. connect all of the gnd connections to as large a copper pour or plane area as possible on the top layer. avoid breaking the ground connection between the external components and the ltm8073. 6. use vias to connect the gnd copper area to the board s internal ground planes. liberally distribute these gnd vias to provide both a good ground connection and thermal path to the internal planes of the printed circuit board. pay attention to the location and density of the thermal vias in figure 3. the ltm8073 can benefit from the heat-sinking afforded by vias that connect to internal gnd planes at these locations, due to their proximity to internal power handling components. the optimum number of thermal vias depends upon the printed circuit board design. for example, a board might use very small via holes. it should employ more thermal vias than a board that uses larger holes. figure 2. the input diode prevents a shorted input from discharging a backup battery tied to the output. it also protects the circuit from a reversed input. the ltm8073 runs only when the input is present. pcb layout most of the headaches associated with pcb layout have been alleviated or even eliminated by the high level of integration of the ltm8073. the ltm8073 is neverthe - less a switching power supply, and care must be taken to ltm8073 v in v in 8073 f02 run ltm8073 8073fa
19 for more information www.linear.com/ltm8073 a pplica t ions i n f or m a t ion hot-plugging safely the small size, robustness and low impedance of ceramic capacitors make them an attractive option for the input bypass capacitor of ltm8073 . however, these capaci - tors can cause problems if the ltm8073 is plugged into a live supply (see linear technology application note 88 for a complete discussion). the low loss ceramic capacitor combined with stray inductance in series with the power source forms an underdamped tank circuit, and the voltage at the v in pin of the ltm8073 can ring to more than twice the nominal input voltage, possibly exceeding the ltm8073s rating and damaging the part. if the input supply is poorly controlled or the ltm8073 is hot-plugged into an energized supply, the input network should be designed to prevent this overshoot. this can be accomplished by installing a small resistor in series to v in , but the most popular method of controlling input voltage overshoot is add an electrolytic bulk cap to the v in net. this capacitors relatively high equivalent series resistance damps the circuit and eliminates the voltage overshoot. the extra capacitor improves low frequency ripple filtering and can slightly improve the efficiency of the circuit, though it is likely to be the largest component in the circuit. thermal considerations the ltm8073 output current may need to be derated if it is required to operate in a high ambient temperature. the amount of current derating is dependent upon the input voltage, output power and ambient temperature. the derating curves given in the typical performance characteristics section can be used as a guide. these curves were generated by the ltm8073 mounted to a 58cm 2 4-layer fr4 printed circuit board. boards of other sizes and layer count can exhibit different thermal behav - ior, so it is incumbent upon the user to verify proper oper - ation over the intended system s line, load and environ - mental operating conditions. for increased accuracy and fidelity to the actual applica - tion, many designers use fea (finite element analysis) to predict thermal per formance. t o that end, page 2 of the data sheet typically gives four thermal coefficients: ja C thermal resistance from junction to ambient jcbottom C thermal resistance from junction to the bot - tom of the product case jctop C thermal resistance from junction to top of the product case jb C thermal resistance from junction to the printed cir - cuit board. while the meaning of each of these coefficients may seem to be intuitive, jedec has defined each to avoid confusion and inconsistency. these definitions are given in jesd 51-12, and are quoted or paraphrased below: ja is the natural convection junction-to-ambient air ther - mal resistance measured in a one cubic foot sealed enclo - sure. this environment is sometimes referred to as still figure 3. layout showing suggested external components, gnd plane and thermal vias sync gnd gnd gnd gnd/thermal vias share pc run v in c in fb bias aux r t r fb c out v out rt tr/ss 8073 f03 ltm8073 8073fa
20 for more information www.linear.com/ltm8073 a pplica t ions i n f or m a t ion air although natural convection causes the air to move. this value is determined with the part mounted to a jesd 51-9 defined test board, which does not reflect an actual application or viable operating condition. jcbottom is the junction-to-board thermal resistance with all of the component power dissipation flowing through the bottom of the package. in the typical module regula - tor, the bulk of the heat flows out the bottom of the pack - age, but there is always heat flow out into the ambient environment. as a result, this thermal resistance value may be useful for comparing packages but the test condi - tions dont generally match the users application. jctop is determined with nearly all of the component power dissipation flowing through the top of the pack - age. as the electrical connections of the typical module regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. as in the case of jcbottom , this value may be useful for comparing pack - ages but the test conditions don t generally match the users application. jb is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the module regulator and into the board, and is often just the sum of the jcbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. the board temperature is measured a specified distance from the package, using a two sided, two layer board. this board is described in jesd 51-9. given these definitions, it should now be apparent that none of these thermal coefficients reflects an actual physi - cal operating condition of a module regulator. thus, none of them can be individually used to accurately predict the thermal performance of the product. likewise, it would be inappropriate to attempt to use any one coefficient to correlate to the junction temperature vs load graphs given in the products data sheet. the only appropriate way to use the coefficients is when running a detailed thermal analysis, such as fea, which considers all of the thermal resistances simultaneously. a graphical representation of these thermal resistances is given in figure 4. the blue resistances are contained within the module regulator, and the green are outside. the die temperature of the ltm8073 must be lower than the maximum rating of 125 c , so care should be taken in the layout of the circuit to ensure good heat sinking of the ltm8073. the bulk of the heat flow out of the ltm8073 is through the bottom of the package and the pads into the printed circuit board. consequently a poor printed circuit board design can cause excessive heating, resulting in impaired performance or reliability. please refer to the pcb layout section for printed circuit board design suggestions. figure 4: graphical representation of the thermal resistances between the device junction and ambient 8073 f04 module regulator junction-to-case (top) resistance junction-to-board resistance junction-to-ambient resistance (jesd 51-9 defined board) case (top)-to-ambient resistance board-to-ambient resistance junction-to-case (bottom) resistance junction ambient case (bottom)-to-board resistance ltm8073 8073fa
21 for more information www.linear.com/ltm8073 typical a pplica t ions 15v out from 19.5v in to 60v in step-down converter. bias is tied to aux 1.2v out from 3.4v in to 60v in step-down converter. bias is tied to an external 3.3v source 2.5v out from 4v in to 15v in step-down converter. bias is tied to v in 1f 100f 118k ltm8073 v out run v out 2.5v 3.3a v in v in 4v to 15v fb gnd bias sync 8073 ta04 pins not used in this circuit: tr/ss, pg, share, aux 51.1k 800khz rt 1f 22f 26.7k 1.4mhz 14.3k ltm8073 v out fb aux bias v out 15v 2.7a v in v in 19.5v to 60v gnd run sync rt 8073 ta02 pins not used in this circuit: tr/ss, pg, share 1f ext 3.3v 100f 2 47pf 499k ltm8073 v out aux v out 1.2v 3.5a v in v in 3.4v to 60v fb gnd run sync 8073 ta03 pins not used in this circuit: tr/ss, pg, share 84.5k 500khz rt bias ltm8073 8073fa
22 for more information www.linear.com/ltm8073 typical a pplica t ions C5v out from 3.4v in to 55v in positive to negative converter. bias tied to ltm8073 gnd maximum load current vs v in , bias tied to ltm8073 gnd use two ltm8073s powered from the same input source to get more output current 1f 100f 47.5k ltm8073 v out run optional schottky diode v in v in 3.4v to 35v fb gnd sync bias 8073 ta05a pins not used in this circuit: tr/ss, pg, share, aux 32.4k 1.2mhz rt + input bulk cap v out ?5v 1f 47.5k 850khz ltm8073 v out fb aux bias v out 3.3v 6.5a continuous 10a peak v in v in 7v to 40v gnd tr/ss run sync optional sync share tr/ss share rt 1f 100f 47.5k 850khz 40.2k ltm8073 v out fb aux bias v in gnd run sync optional sync rt 8073 ta06 pin not used in this circuit: pg 100f ltm8073 8073fa 3 4 5 maximum load current (a) 8073 ta05b input voltage (v) 0 20 40 60 0 1 2
23 for more information www.linear.com/ltm8073 p ackage descrip t ion p ackage p ho t os table 3. ltm8073 pinout (sorted by pin number) pin name pin name pin name pin name pin name pin name pin name pin name a1 gnd b1 fb c1 gnd d1 gnd e1 gnd f1 gnd g1 v out h1 v out a2 bias b2 aux c2 gnd d2 gnd e2 gnd f2 gnd g2 v out h2 v out a3 pg b3 gnd c3 v in d3 gnd e3 gnd f3 gnd g3 v out h3 v out a4 share b4 sync c4 v in d4 gnd e4 gnd f4 gnd g4 v out h4 v out a5 rt b5 tr/ss c5 v in d5 gnd e5 gnd f5 gnd g5 v out h5 v out a6 gnd b6 run c6 v in d6 gnd e6 gnd f6 gnd g6 v out h6 v out ltm8073 8073fa
24 for more information www.linear.com/ltm8073 p ackage descrip t ion please refer to http://www.linear.com/product/ltm8073#packaging for the most recent package drawings. notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jep95 5. primary datum -z- is seating plane 6. solder ball composition is 96.5% sn/3.0% ag/0.5% cu 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature package top view 4 pin ?a1? corner x y aaa z aaa z package bottom view 3 see notes suggested pcb layout top view bga 48 0217 rev a ltmxxxxxx module tray pin 1 bevel package in tray loading orientation component pin ?a1? pin 1 0.000 0.5 0.5 1.5 1.5 2.5 2.5 3.5 0.5 2.5 1.5 0.5 1.5 2.5 3.5 0.000 detail a ?b (48 places) f g h e a b c d 2 1 4 3 56 detail b substrate // bbb z d a a1 b1 ccc z detail b package side view mold cap z m x yzddd m zeee 0.50 0.025 ? 48x symbol a a1 a2 b b1 d e e f g h1 h2 aaa bbb ccc ddd eee min 3.12 0.40 2.72 0.50 0.47 0.27 2.45 nom 3.32 0.50 2.82 0.60 0.50 9.00 6.25 1.00 7.00 5.00 0.32 2.50 max 3.52 0.60 2.92 0.70 0.53 0.37 2.55 0.15 0.10 0.20 0.25 0.10 notes ball dimension ball ht substrate thk mold cap ht pad dimension dimensions total number of balls: 48 e b e e b a2 f g bga package 48-lead (9mm 6.25mm 3.32mm) (reference ltc dwg # 05-08-1999 rev a) h1 h2 7 package row and column labeling may vary among module products. review each package layout carefully ! 7 see notes detail a ltm8073 8073fa
25 for more information www.linear.com/ltm8073 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 08/17 changed recomended bias pin connection from open to ltm8073 gnd for the negative voltage output application. updated derating curves. changed minimum storage temperature from C50c to C55c. 5, 8, 9, 13, 22 8, 9 2 ltm8073 8073fa
26 for more information www.linear.com/ltm8073 ? linear technology corporation 2017 lt 0817 rev a ? printed in usa www.linear.com/ltm8073 r ela t e d p ar t s typical a pplica t ion 1v out from 3.4v in to 60v in step-down converter with spread spectrum. bias is tied to an external 3.3v source design r esources subject description module design and manufacturing resources design: ? selector guides ? demo boards and gerber files ? free simulation tools manufacturing: ? quick start guide ? pcb design, assembly and manufacturing guidelines ? package and board level reliability module regulator products search 1. sort table of products by parameters and download the result as a spread sheet. 2. search using the quick power search parametric table. techclip videos quick videos detailing how to bench test electrical and thermal performance of module products. digital power system management linear technologys family of digital power supply management ics are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature eeprom for storing user configurations and fault logging. 1f 100f 2 47pf ltm8073 v out fb aux v out 1v 3.4a v in v in 3.4v to 60v ext 3.3v gnd run rt 8073 ta07 pins not used in this circuit: tr/ss, pg, share 95.3k 450khz bias sync part number description comments ltm8050 58v, 2a step-down module regulator 3.6v v in 58v, 0.8v v out 24v, 9mm 15mm 4.92mm bga ltm8027 60v, 4a step-down module regulator 4.5v v in 60v, 2.5v v out 24v, 15mm 15mm 4.92mm bga ltm8064 58v, 6a cvcc step-down module regulator 6v v in 58v, 1.2v v out 36v, 11.9mm 16mm 4.92mm bga ltm8056 58v in , 48v out buck-boost module regulator 5v v in 58v, 1.2v v out 48v, 15mm 15mm 4.92mm bga ltm8053 40v, 3.5a/6a step down silent switcher module regulator 3.4v v in 40v, 0.97v v out 15v, 6.25mm 9mm 3.32mm bga LTM8003 ltm8053 with h-grade (150c operation) and fmae compliant pinout 3.4v v in 40v. 0.97v v out 18v, 6.25mm 9mm 3.32mm bga ltm8032 36v, 2a low emi step-down module regulator 3.6v v in 36v, 0.8v v out 10v, en55022b compliant ltm8033 36v, 3a low emi step-down module regulator 3.6v v in 36v. 0.8v v out 24v, en55022b compliant ltm8073 8073fa

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